![]() ![]() That is to say, it simply generates more hardware elements (gates), and does not inform process flow. If I may summarize/clarify the first statement though, the 'for' statement in an HDL simply expresses 'syntactic replication' not 'sequential execution'. answer is impresively thorough and quite accurate. Parallel-in/ serial-out shift registers do everything that the previous serial-in/ serial-out shift registers do plus input data to all stages simultaneously. This means that maybe something like this is a good idea: shiftcounter:= 0 tempreg shiftcounter:= shiftcounter + 1 sout = n-1) then state '0') TYPE POSSIBLESTATES IS (waiting, shifting) signal state: POSSIBLESTATES begin process(clk,reset) variable shiftcounter: integer:= 0 begin if(reset = '1') then tempreg '0') state shiftcounter:= 0 tempreg shiftcounter:= shiftcounter + 1 sout = n-1) then state. The state signal definition: TYPE POSSIBLESTATES IS (waiting, shifting) signal state: POSSIBLESTATES In the process proper: case state is when waiting = Ok, so what happens when we're waiting for an enable? It would be a good idea to set all (driven) variables to a known value. ![]() Perhaps a wait state for when the process is not shifting, and a shifting state for when it is. ![]()
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